1. Field of the Invention
This invention relates to the field of microprocessors, and in particular to microprocessors having an extended address space.
2. Description of Related Art
An 8-bit data structure and 16-bit address structure has been, and continues to be, a common architecture for low cost microprocessors, or microcontrollers, such as the 80C51 family of processors, and others, that have a legacy that extends back for decades. During these decades, a number of software/firmware applications and routines have been developed.
To remain competitive, application developers continually add features and functions to devices that use microprocessors. Unfortunately, the 16-bit address structure of common processors limits the size of programs, or the amount of data, that can be embodied within these devices. Larger capacity devices, such as 32-bit processors, can address a larger program or data space, but are typically more expensive than conventional 8-bit processors. Moving an existing application from one processor family to another in order to provide a larger addressable space for adding additional features, however, typically requires a substantial investment. The development personnel must be trained to use the new processor; libraries of xe2x80x9cutility programsxe2x80x9d, such as mathematical routines and interrupt routines, must be rewritten for the new processor; time-dependent routines must be tested and verified on the new processor; idiosyncratic behavior of the new processor must be discovered and overcome; and so on.
Expanding the addressing space of an existing processor alleviates a number of the difficulties associated with a transition to a new processor, but also introduces a number of compatibility issues with applications and routines that were developed for the existing shorter-address processor. Consider, for example, the effect of a larger addressing space on the operation of a conventional stack. When a subroutine is called, the location of the address to which the subroutine should return is xe2x80x9cpushedxe2x80x9d onto the stack. When a return is executed from the subroutine, the appropriate number of bytes must be xe2x80x9cpoppedxe2x80x9d off the stack. The number of bytes popped off the stack corresponding to an address must equal the number of bytes pushed onto the stack. A straightforward solution would be to always push the largest number of address bytes onto the stack, and to always pop this largest number of bytes off the stack. As is known in the art, however, stack resources are often limited, and, because stack utilization is dynamic and often condition-dependent, a maximum required stack size is difficult, and sometimes impossible, to determine. This is particularly problematic with regard to interrupt-driven processes. Each time an interrupt is received, the xe2x80x98next-addressxe2x80x99 is pushed onto the stack and an address associated with the processing of the particular interrupt becomes the xe2x80x98next-addressxe2x80x99. If the interrupt calls another process, another address is pushed onto the stack. These addresses remain on the stack until the process associated with the interrupt is completed. If an additional interrupt occurs before the original interrupt is completed, one or more additional addresses will be pushed onto the stack. If an address is pushed onto the stack beyond the limits of the stack (a xe2x80x9cstack-overflowxe2x80x9d error), unpredictable results will occur. As is also known in the art, stack overflow errors are extremely difficult to diagnose. Increasing each pushed and popped address from two bytes (16-bits) to three bytes could amount to a 50% increase in stack utilization. Such a large increase in stack utilization may preclude the use of this technique for a number of legacy applications, due to the increased likelihood of stack overflow errors.
It is an object of this invention to provide a processing system and method that allows for extended memory addressing while maintaining compatibility with legacy devices. It is a further object of this invention to provide a processing system and method that allows for a dynamic control of stack allocation and utilization. It is a further object of this invention to provide a processing system and method that allows for a dynamic control of stack allocation and utilization for interrupt processing.
These objects and others are achieved by providing a processing system with extended addressing capabilities, and with a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.